1. Field of the Invention
The present invention relates to a memory device with a data output buffer and the control thereof, and more particularly, to a memory device which outputs the read data from the memory cell array without error and provides sufficent time in outputting the data, and the control method thereof.
2. Discussion of Related Art
In general, it is preferable to transfer accurately the read data from the memory device to the external system. To accomplish such a stable operation, it is required to maintain in a stable state the driving capability or operating state of the memory device. However, the driving capability of the memory device generally is varied by the variations of the pheripheral temperature or the driving voltage.
On account of such reasons, the data state outputted from the output buffer of the memory device may be unstable. That is, characteristics of the transistors may be unstable and the operating time of the clock signals generated in the memory device may be inaccurate. Therefore, if the operating time is unstable, the time interval of the output data is varied. In connection with this phenomenon, a data window time is defined, which denotes the time interval for acquiring a stable data. In general, the data window time has been much more important as the data process speed has improved, i.e., as the operation speed of the memory device has been enhanced.
FIG. 1 is a block diagram of a conventional memory device, and is shown to explain the output process which outputs the data within the memory device through a plurality of pipe means to the data output buffer. Hereinbelow, the conventional data output method will be described in detail with reference to FIG. 1. Although FIG. 1 shows Synchronous DRAM which has a pipe function, any other various storing devices, such as general DRAM or registers which can store data, may be applicable to this case.
As shown in FIG. 1, the clock input buffer 1 receives an external clock, and generates an internal clock which has a preferable voltage level necessary to the operation of the memory device.
The pipe counter generator 2 receives the internal clock outputted from the clock input buffer 1. The pipe counter generator 2 also receives a plurality of pipe counter enable signals pcnt-en0, pcnt-en1, and pcnt-en2 which are determined in relation to the CAS latency and burst length.
Wherein, the CAS latency indicates a time interval between the timing when the external clock is inputted and the timing when the data is outputted through the data output buffer of memory device, and generally is expressed as the number of the inputted external clocks until the output timing of the data from the memory device. Accordingly, the CAS latency is related to the speed of the data process.
The burst operation processes to generate sequentially a series of commands by a certain specified command. The operation speed of the memory device is increased by the burst operation which is one of the sequential burst and interleave burst operations. In general, the burst operation is used to generate a series of addresses in memory device. In this case, the number of the generated addresses is a burst length.
The pipe counter generator receives the internal clock and a plurality of pipe counter enable signals pcnt-en0, pcnt-en1, and pcnt-en2; and outputs a plurality of pipe counter signals pcnt0, pcnt1, and pcnt2. The pipe counter signals pcnt0, pcnt1, and pcnt2 are delayed by the CAS latency and controls the pipe latch circuit 3.
The pipe latch circuit 3 latches the data read from memory cell array during the read mode of the memory device. The data are inputted to the pipe latches of the pipe latch circuit 3. The pipe latch circuit 3 latches the received data during a specified time. The latched data in the pipe latches are selectively outputted in response to the pipe counter signals.
As shown in FIG. 1, the signals pl-out outputted from the pipe latch circuit are inputted to the data output buffer means 4 which includes many data output buffers. The data output buffer means stores and buffers the signals, i.e. the data RD, during a specified time.
FIGS. 2a to 2d are detailed circuits of a block diagram in FIG. 1.
FIG. 2a is a circuit diagram of the clock input buffer in FIG. 1. As shown in FIG. 2a, the clock input buffer includes a differential amplifier and a current mirror circuit. Therefore, the clock input buffer 1 compares the external clock ext.sub.-- clk with the reference voltage Vref, and also converts the voltage level of the external clock into a CMOS voltage level which is used as the level of the internal clock.
FIG. 2b is a circuit diagram of the pipe counter generator 2 in FIG. 1. As shown in FIG. 2b, the pipe counter generator receives the internal clock outputted from the clock input buffer. The internal clock is inputted at the drain terminal of the transistor N1. The pipe counter enable signals are inputted at the gate terminal of the transistor N1. The pipe counter generator 2 outputs the pipe counter signals pcnt0, pcnt1, and pcnt2 in response to the internal clock and the pipe counter enable signals pcnt.sub.-- en0, pcnt.sub.-- en1, and pcnt.sub.-- en2. If the reset signal is activated, output of the pipe counter signals pcnt0, pcnt1, and pcnt2 are disabled with low level. Namely, the PMOS P1 and NMOS N1 transistors of the pipe counter generator 2 maintains the initial state of the generator with low level Vss during the standby mode. FIG. 2c is a pipe latch circuit shown in FIG. 1, and includes flip-flops in order to latch the data RD outputted from the memory cell array. The pipe counter signals pcnt0, pcnt1, and pcnt2 control the corresponding flip-flops to output the data in sequence.
The data pl.sub.-- out outputted from the pipe latch circuit 3 are inputted to the data output buffer.
FIG. 2d shows circuit diagram of the data output buffer. The data output buffer 4 stores the output data pl.sub.-- out from the pipe latch circuit 3 and outputs the data to external systems.
FIGS. 3a to 3h are waveform diagrams in the prior art.
FIG. 3a is a waveform of the external clock Ext.sub.-- clk, and FIG. 3b is a waveform of the internal clock Int.sub.-- clk. FIGS. 3c to 3e are waveforms of the pipe counter enable signals pcnt.sub.-- en0, pcnt.sub.-- en1, and pcnt.sub.-- en2. FIG. 3f is data read from the memory cell array. FIG. 3g is the waveform of the output from the pipe latch circuit, and FIG. 3h is output from the data output buffer.
In FIG. 3, CAS latency is 3 and burst length is 4. In other words, because the data in FIG. 3h are not outputted until the number of the external clock inputted in FIG. 3a is 3, CAS latency is 3. Further, as shown in FIG. 3f, because four data are continually outputted from the memory cell array, burst length is 4. The reason is that four addresses are continually generated in memory device in response to one address which is inputted externally.
As shown in FIGS. 2 and 3, the reset of the pipe counter signal pcnt0 is determined by the pipe counter signal pcnt1, the reset of the pipe counter signal pcnt1 is determined by the pipe counter signal pcnt2, and the reset of the pipe counter signal pcnt2 is determined by the pipe counter signal pcnt0. The lines at the rising and falling edges of the clocks indicate the variation of the operation timing which is caused by the variations of the temperature and/or voltages of the pheripheral circuit.
In general, a clock access time tAC, a data window time tDW, and a output hold time tOH are varied by the variations of the temperature and/or voltages.
In particular, the reasons of the variation of the clock access time tAC are as follows. The first reason is that the transfer speed is varied by the variation of the characteristics of the transistors while the external clock passes through the clock input buffer, the pipe counter, and the pipe latch circuit. The second reason is that the transfer speed is varied by the different locations of the data output buffers.
The output hold time tOH indicates a time interval from the timing when the external is applied to the timing when the data in output buffer is replaced with a new data. Accordingly, the output hold time tOH is also varied by the variation of the characteristics of the transistors, which is caused by the variation of the voltage and/or temperature.
The clock access time tAC indicates a time interval t1-t2 from the timing when the external clock is applied at time t1 to the timing when the first data is outputted last by the variation of the pheripheral characteristic t2. At worst, if the voltage source is lowered and the temperature is increased, the clock access time tAC is the longest.
The output hold time tOH indicates a time interval t3-t4 from the timing when the external clock is applied at time t3 to the timing when the first data is latched most shortly in the data output buffer by the variation of the pheripheral characteristic. At worst, if the voltage source is increased and the temperature is decreased, the output hold time tOH is the shortest. The data window time indicates a time interval t2-t4. The t2 indicates the timing when the data is outputted last by the variation of the pheripheral characteristic, and the t4 indicates the timing when the data is latched in short time by the variation of the pheripheral characteristic.
As described above, the worst cases from are that access time tAC and output hold time tOH are different each other. In addition, the data window time which indicates data latching time in the data output buffer may be unstable by the variation of voltage and/or temperature in the internal circuit. Also, an erroneous operation of a memory device may be caused by the shortened data window time.